In recent years, to deter the worsening of short-channel effects generated by greater chip down-sizing, C. Mazure, etc. and H. Kotaki, etc. proposed employing elevated source/drain chip structure in reducing the source/drain junction depth as a method in preventing short-channel effects, refer to 1992 IEDM, December Issue, pp. 853-856, and 1993 IEDM, December Issue, pp. 839-842 respectively. The most commonly reported method of forming elevated source/drain is selective epitaxial growth(SEG) in the exposed source/drain sector.
Local interconnection is an effective means in enhancing the efficiency of circuit layout which is commonly applied in SRAM; it can be used to connect the neighboring source/drain and gate to consolidate the SRAM layout in reducing the silicon real estate. As documented in 1987 IEEE Trans. Electron Devices, March Issue, Page 682 by T. Tang and etc., the most common local interconnection is achieved by using TiN, a byproduct in producing TiSi.sub.2, for selective masking and etching. The advantage of this method is utilizing the existing TiN without any further deposition procedure except an additional micro-etching to achieve the required local interconnection. However, the drawback is that the resistance of TiN is 10 times higher than TiSi.sub.2 and only suitable for TiSi.sub.2 system; it cannot be applied in CoSi.sub.2 as TiN is not a byproduct derived from producing cobalt.